1. Field of the Invention
The present invention relates to a semiconductor process and, more particularly, to a method of forming a bitline contact hole and interconnection contact holes.
2. Description of the Related Art
When manufacturing memory products such as trench-type DRAM, stacked-type DRAM and FLASH memory, in order to reduce the size of a chip, the conventional semiconductor process uses self-aligned contact (SAC) technology to define a reduced distance between two adjacent gate conductive structures.
FIGS. 1A to 1F are sectional diagrams showing a conventional method of forming contact holes using SAC process. As shown in FIG. 1A, a P-type silicon substrate 10 is provided with plurality of shallow trench isolation (STI) regions 12 in the substrate 10 to isolate adjacent active areas (AA), a gate insulating layer 14 formed on the substrate 10, a plurality of gate conductive structures 161, 162, 163 and 164 patterned on the gate insulating layer 14, and a plurality of N−-type ion implantation regions 20 formed in the substrate 10 and at lateral regions of the gate conductive structures 161˜164. Each of the gate conductive structures 161˜164 is stacked by a polysilicon layer 17, a tungsten silicide layer 18, and a silicon nitride cap layer 19.
As shown in FIG. 1B, a silicon oxide spacer 22 is grown on the sidewalls of the polysilicon layer 17 and the tungsten silicide layer 18, and then a silicon nitride spacer 24 is formed on the sidewalls of the gate conductive structures 161˜164. Next, using ion implantation with the gate conductive structures 161˜164 and the silicon nitride spacer 24 as the mask, an N+-type ion implantation region 26 is formed in the exposed N−-type ion implantation region 20. Thereby, the N+-type ion implantation region 26 serves as a source/drain region, and the remaining N−-type ion implantation region 20 serves as a lightly doped drain (LDD) structure.
As shown in FIG. 1C, a SiON liner 28 is deposited on the entire surface of the substrate 10, and then an inter-layered dielectric (ILD) layer 30 with a planarized surface is formed on the SiON liner 28 to fill the gaps between adjacent gate conductive structures 161˜164 by deposition and chemical mechanical polishing (CMP). Preferably, the ILD layer 30 is boro-phspho silicate glass (BPSG), high density plasma (HDP) oxide, tetraethylorthosilicate (TEOS), or their combination.
Next, as shown in FIG. 1D, using a first photoresist layer 31 with a pattern of the bitline contact hole as the mask, parts of the ILD layer 30 and the SiON liner 28 between the two gate conductive structures 162 and 163 are removed to expose the N+-type ion implantation region 26, thus a bitline contact hole 32 is formed.
Thereafter, as shown in FIG. 1E, after removing the first photoresist layer 31, a first conductive layer is deposited to fill the bitline contact hole 32 and then etched back to a predetermined height within the bitline contact hole 32, thus the first conductive layer remaining in the bitline contact hole 32 serves as a bitline contact plug 34.
As shown in FIG. 1F, using a second photoresist layer 35 with a pattern of interconnection contact holes as the mask, parts of the ILD layer 30, the SiON liner 28 and the silicon nitride cap layer 19 is etched to form a first interconnection contact hole 36 and a second interconnection contact hole 38. The first interconnection contact hole 36 is formed over the first gate conductive structure 161 to expose the surface of the tungsten silicide layer 18. The second interconnection contact hole 38 is formed outside the gate conductive structure 164 to expose the N+-type ion implantation region 26. Finally, the second photoresist layer 35 is removed.
However, the above-described SAC process has disadvantages as listed below. First, when a larger step height between AA and STI, misalignment during photolithography, or CMP cannot provide the ILD layer 30 with an appropriate thickness and superior flatness, the etched profile of the contact hole is affected, causing problems of the interconnection structure, such as a short circuit between bitline and wordline or a blind window in the bitline contact hole 32, especially for design rule shrinking more and more. Second, since the etching selectivity from the ILD layer 30 to the SiON liner 28 is not large enough to provide etching stop capability during the formation of the bitline contact hole 32, seams can form in the STI region 12 to cause junction leakage between the bitline contact plug following formed and the substrate 10. Third, the silicon nitride cap layer 19 requires thicker thickness in the SAC process, thus thermal budget is increased and electrical properties, such as Vt, Idsat, Ioff, are worsened. Fourth, if the SAC process is applied to manufacture a device of further reduced size, the problems encountered in photolithography and etching become more difficult. Fifth, the materials used for the cap layer 19 and the spacer 24 are limited to SiN or SiON, resulting in worsening of the leakage problem in the polysilicon layer 17.